In Figure 3, a photo of the board is shown. And this is complicated to achieve with 96 traces. This adds a slight complexity to the layout but is required to reach these high-speed with a parallel interface.Īs mentioned in section II, the traces lengths of the data lanes also need to be matched to limit the bit to bit skew. Adding to that, in order to limit the package skew which is different for each bit, every group of 12 bits (24 traces with differential signaling) is layout to the same bank of the FPGA. ![]() Moreover, at this speed, differential signaling is necessary and a total of 96 PCB traces are layout between FPGA and DAC through multiple layers. The DAC having a resolution of 12 bits plus its 4:1 MUX, it means that there are 48 bits to interface.
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